This invention relates to memory arrays and, more particularly, to semiconductive memory cell designs suitable for fabrication in large-scale-integrated (LSI) form.
In recent years considerable effort has been directed at devising memory arrays that can be made as LSI chips with a minimum of processing complexity. This effort has resulted in a variety of proposals for relatively simple memory cell designs. A particularly simple such memory cell is described in U.S. Pat. No. 3,876,992. Each individual memory cell in U.S. Pat. No. 3,876,992 comprises a single transistor and an associated capacitor.
Despite the simplicity of the cells shown in U.S. Pat. No. 3,876,992, the fabrication of those cells in LSI form in a memory array does not result in as small an array area as is desired in some applications of practical importance. Moreover, the processing required to form such an LSI array is relatively complicated. In addition, the complex voltage waveform that must be applied to the word lines of the array during writing and reading operations complicates the design of the overall array.
Accordingly, the need arose for a simple small-area memory cell that could be more easily made in LSI form and operated by the application thereto of relatively simple waveforms. It was recognized that such a cell, if available, would enable the fabrication of improved LSI memory arrays.